1. Field of the Invention
The invention relates to a method for manufacturing a semiconductor device.
2. Background Art
Technology of forming three-dimensionally arranged memory cells, which includes creating through-holes from the uppermost layer to the bottom layer in a stacked structure in which a plurality of conductive layers function as word electrodes in a memory device and a plurality of dielectric layers are alternately stacked, forming a charge storage layer on the inner wall of the through-hole, and filling silicon into the through-hole in pillar shape, is proposed in, for example, JP-A 2007-266143 (Kokai).
When forming through-holes in a stacked structure of a plurality of conductive layers and a plurality of dielectric layers, it is necessary to alternately process (etch) the conductive layers and the dielectric layers. At this time, there may be a method in which the conductive layers are processed by forming a mask layer having an etching selection ratio to the conductive layers and using a processing apparatus for the conductive layers, and the dielectric layers are processed by forming a mask layer having an etching selection ratio to the dielectric layers and using a processing apparatus for the dielectric layers. However, the number of stacked conductive layers and dielectric layers are expected to increase in the future, and in this case, processing the conductive layers and the dielectric layers alternately by using separate processing apparatuses imposes a heavy burden of cost. Therefore, the hole formation is preferably performed collectively in a same chamber.
In the case where a mask layer of, for example, silicon oxide type is used when forming holes collectively, the mask layer has a sufficient etching selection ratio to silicon-based conductive layers. However, when etching dielectric layers of the same silicon oxide type, the mask layer is also etched to the same degree as the dielectric layers. The mask layer can be formed thick in anticipation of the degree of etching. Here, when the number of stacked conductive layers and dielectric layers further increases, the etching amount of the mask layer increases depending on the number of dielectric layers. Accordingly, the mask layer needs to be made thicker for the etching amount of the dielectric layers. However, the increase in the thickness of the mask layer imposes high aspect ratio to form pattern openings in the mask layer, and there is concern that the processing of the mask layer itself becomes difficult.